The invention relates to an efficient topography for a CMOS microcomputer including a sixteen bit static low power CMOS microprocessor, 8192 bytes of ROM, 576 bytes of RAM, eight chip select outputs, eight 16 bit timers with maskable interrupts, four UARTs, 29 priority encoded interrupts, built in de-bug features, a bus control register for external memory bus control, interface circuitry for I/O devices, time of day clock features, twin tone generators, a bus control register for external memory bus control, an abort input for low cost virtual memory interface, a high performance interrupt driven parallel bus interface, and system speed control circuitry to allow the microprocessor access to both slow and fast memories and I/O interface and to effectuate automatic reduction of overall system power.
My U.S. Pat. Nos. 4,652,992 and 4,739,475 fully describe the topography and logic circuitry of commercially available processors known as the W65C602S and W65C816S microprocessors, respectively. My U.S. Pat. No. 5,123,107 issued Jun. 16, 1992 entitled "TOPOGRAPHY OF CMOS MICROCOMPUTER INTEGRATED CIRCUIT CHIP INCLUDING CORE PROCESSOR AND MEMORY, PRIORITY, AND I/O INTERFACE CIRCUITRY COUPLED THERETO", incorporated herein by reference, fully describes the topography of a microcomputer integrated circuit chip, known as the W65C134S, including a W65C602S as a "core" processor, and also including memory, priority, and I/O interface circuitry coupled to the core microprocessor. Microprocessors generally contain an internal address bus, an internal data bus, a number of registers including an accumulator, a program counter, an internal data latch, stack pointer registers, index registers, an arithmetic logic unit, an instruction register, a status register, and instruction decoding circuitry, register transfer logic, and data buffer latches and address latches. Microprocessors do not ordinarily contain additional components that are needed in a microcomputer system, such as a read only memory for storing programs, a random access memory for storing variables and data, timers, UARTs, I/O functions, priority interrupt systems and the like. However, with the wide availability and commercial success of quite a number of microprocessors, various suppliers have begun using commercially available microprocessor designs as "embedded" cores of larger microcontrollers or microcomputers on single silicon chips that include not only the microprocessor, but also some or all of the above-mentioned components and other components.
The foregoing integrated circuit topography design considerations and constraints make it a considerable challenge to design a microcomputer or microcontroller utilizing an already designed layout for the microprocessor "core" section. Positioning of the core microprocessor, the ROM, RAM, UART, timers, bus control register, and interface circuitry, etc. must be accomplished in such a way as to allow the microprocessor to interface easily on a printed circuit board with other ASIC's (applications specific integrated circuits) designed by the user to implement a larger system. Difficult tradeoffs must be established between the often opposing objectives of (1) minimizing total semiconductor area occupied by the microcomputer and (2) making connection to many leads of the microcomputer which have to be located in certain positions for reasons that are unrelated to minimizing microcomputer chip area.
In some applications of a microcomputer it may be desirable to access off-chip memory, such as slow EPROM, SRAM or DRAM and fast on-chip SRAM and SROM. It would be very desirable for the entire microcomputer to be able to automatically operate at various fast and slow speeds while accessing various on-chip and off-chip memories and/or peripheral devices, because many applications of microcomputers require use of battery power, and consequently it would be very desirable for microcomputers used in such applications to be able to automatically minimize the system power consumption according to the demands of the program or routines currently being executed. Conventional computers continue to operate at a fast cycle rate during a slow memory access, using wait states or the like to effectuate accessing of slower blocks of memory to allow the processor to continue to perform functions.
The closest prior art known to me is the W65C134S microcontroller, fully described in above U.S. Pat. No. 5,123,107, which I designed and now market through my company, The Western Design Center, Inc. of Mesa, Ariz. The function and topography of the W65C134S was a substantial improvement over the earlier W65C124S, which did not succeed in adequately meeting the objectives of a general purpose microcomputer that can be easily interfaced to a wide variety of ASIC's or other circuitry likely to be required by a user in implementing a larger microcomputer system.
There is a presently unmet need for an efficient topography for a microcomputer including the W65C816S or other CMOS microprocessor and a variety of peripheral ROM, RAM, UART, priority interrupt, and other functions on a single chip. There is a presently unmet need for a more powerful microcomputer that can operate with lower power consumption than previously has been practical.